1. Field of the Invention
The present invention relates generally to a system of processing graphic or pattern data using a computer. More particularly, this invention relates to a system of processing circuit component pattern data according to the design requirement of a semiconductor integrated circuit design.
2. Description of the Related Art
One way to manage the vast amount of data necessary for computer aided design (CAD) of semiconductor circuit is to separate the data into reasonable sized data segments for separate data processing. Data management of this type not only increases data processing efficiency, but also decreases overall semiconductor design time and design costs. Segmented data processing, when designing complex circuit, further allows for enhanced manipulation of the many and various types of data. Moreover, computer aided circuit design often requires selection of individual circuit component patterns. Utilizing segmented data processing further increases the ability of the circuit designer to select individual circuit patterns for further data processing.
Most CAD systems today are capable of selecting individual circuit component patterns or groups of patterns to facilitate the design process. This function is in particular helpful to check whether one or more design patterns meet design requirements, as is done with the so-called design rule check (DRC). To perform this type of error checking, the circuit designer selects a portion of the layout design using a technique called windowing. Windowing is typically performed by the circuit designer manipulating a mouse or other computer input device to select a portion of the layout design displayed on a computer monitor or other device. With one portion of the design layout selected or windowed, the CAD program can then perform data processing on that portion of the design wholly or partially within the selected window. The type of data generally used for this includes circuit component and layout data, substrate layer data and window coordinate data. Rectangular pattern of a design layout can be defined by the coordinate values of the individual vertexes of the rectangular pattern.
FIG. 1 shows the layout of circuit components of a semiconductor chip 186 used for a semiconductor device 185. The semiconductor chip 186 has a plurality of functional circuit blocks B1 to B5 arranged at the center, and a number of pads 187 surrounding the circuit blocks B1-B5. Each of the circuit blocks B1-B5 has circuit component patterns laid out for that block. The individual circuit blocks B1-B5 when connected by interconnection patterns form the semiconductor device 185.
A layout check for the semiconductor chip 186 is performed to check the integrity of the interconnection patterns and to check the component patterns forming the circuitry in each of the blocks B1-B5. Typically, the circuit designer designates a portion of the circuit design for the system to check. By specifying two points on the design, the CAD system can generate a rectangular window based on an orthogonal line connecting the two points. For example, as shown in FIG. 1, once points P1 and P2 are selected, the CAD system generates a window 188. In similar fashion, points P3 and P4 demarcate a window 189, points P5 and P6 demarcate a window 190, and points P7 and P8 demarcate a window 191. Next, the CAD system identifies the pattern data design contained either entirely or partially in each of the windows 188 to 191, and executes a desired process on the identified pattern data. Window designation allows the CAD system to limit the amount of data processing to only those patterns in need of processing. Designating multiple windows for larger circuit designs permits the CAD system to perform pattern data processing one window at a time. Segmented data processing like this allows the CAD system to store the results of the processing on each data segment, conserves computer resources, and increases data processing speed.
The above described pattern of data processing, however, experiences problems when portions of the pattern data, identified as being within the window, are located near the boundary of the window. Suppose, as shown in FIG. 2, a pattern 193 and a pattern 194 overlap each other in order to form a single combined pattern only a part of the pattern 193 is included in the window 192. Therefore, the CAD system will identify the pattern 193 rather than the combined pattern (193, 194) for pattern data processing. This misidentification causes erroneous data processing.
An additional problem for CAD processing based on conventional windowing techniques relates to the accuracy of the distance detected between patterns in the layout of semiconductor designs. This will be explained with reference to FIGS. 3 through 7.
In step 160 in the flowchart in FIG. 3, the CAD system initially processes prepared input data descriptive of a circuit component pattern and stores the input data in a file. FIG. 4A, for example, illustrates a pattern group 170 consisting of nine patterns 171 to 179. The same pattern group is shown in FIG. 4B having a windowed shade area 180 superimposed on a portion of the pattern group 170. Coordinates P20 and P21 of the window 180 can be preset by the circuit designer or selected by means of an input device such as a mouse or keyboard (not shown). Following the designation of the window 180, the CAD system identifies data descriptive of the patterns 174, 176, 178 and 179 positioned entirely or partially in the window 180, as shown in FIG. 4C. Data descriptive of patterns wholly outside the window is not processed. The CAD system next stores the windowed data in an associated file, and releases the designation of the window 180.
In step 161, the CAD system detects and eliminates overlapping portions of the patterns identified in step 160. Pattern overlap is typical of semiconductors formed with superimposed layers of patterns, each having their own individual pattern data. Thus, as shown in FIG. 5A, the patterns 178 and 179 are two patterns among the windowed pattern data 174, 176, 178 and 179 that overlap each other. By executing a logical OR operation relative to the patterns 178 and 179, the CAD system eliminates the overlap pattern from the two patterns and creates a single pattern 182, as shown in FIG. 5B. The CAD system then stores the data of the patterns 174, 176 and 182 in a system file.
In step 162, the CAD system checks the distance between the individual patterns against system design specifications. In particular, the CAD system reads the data describing patterns 174, 176 and 182 from the system file, identifies the distances between the patterns as shown in FIG. 6A and compares the distances against the design specifications. When the distance D1 or D2, as shown in FIG. 6A, is determined to be smaller than required by the design specifications, the CAD system considers the design layout flawed. Upon this occurrence, the CAD system generates a layout error indication pattern between the patterns not meeting design specifications. In the example shown in FIG. 6C, layout error indication patterns 183 and 184 are generated between patterns 174, 176 and 174, 182, respectively. The CAD system then stores the data describing the patterns 174, 176 and 182 as well as data describing layout error indication patterns 183 and 184 in a single system file.
The CAD system then, at step 163, integrates data describing the layout error indication patterns 183 and 184 with data describing the patterns 171 to 179 to produce data descriptive of a processed pattern group. This data may then be displayed on a display screen or the like for the benefit of the circuit designer.
Even when the patterns 174, 175 and 176 as shown in FIG. 7 should be handled as a single combined pattern, however, conventional CAD systems generate an error indication pattern 183 between the patterns 174 and 176. Since the error indication pattern 183 is wholly included in the pattern 175, the pattern 183 is not necessary. This unfortunately forces the circuit designer to check whether each of the generated error indication patterns is proper or necessary, referring to the error indication patterns 183 and 184 on the display screen. This is caused by the pattern 175 being between the patterns 174 and 176 but outside of the designated window 180. Conventional CAD systems are not designed to automatically remove unnecessary error indication patterns from the pattern group or to identify necessary error indication patterns. This often forces the circuit designer to check all the error indication patterns on the display, reducing the efficiency of the circuit design process.
To date, conventional CAD systems have had great difficulty in processing pattern data organized according to some data management systems. Examples of how data is organized according to three well known types of management systems are shown in FIGS. 8A, 9A and 10A. FIG. 8A illustrates a first arrangement of data in which circuit component pattern data is hierarchically arranged. FIG. 9A illustrates a second system in which circuit component pattern data is segmented. FIG. 10A illustrates a third system in which circuit component pattern data is arranged at random.
The data group shown in FIG. 8A includes upper rank pattern data H1 and first and second lower rank pattern data H2 and H3. If a CAD system identifies the data H3 by window designation, the CAD system then processes data H3 to generate new pattern data H4. It then replaces the old data H3 with the new data H4, as shown in FIG. 8B. Usually, this data replacement is trouble free, since each of the data H1, H2 and H3 is separated or independent from each other. Accordingly, pattern data arranged as shown in FIGS. 8A and 8B is easily enough processed by conventional CAD systems.
The data group shown in FIG. 9A includes a plurality of data of segmented patterns R1 to R4. These patterns are obtained by dividing a single circuit design layout into four areas. The data group further includes information managing data for managing the four segmented pattern data. If a CAD system identifies the fourth segmented pattern data R4 by window designation, the CAD system then processes data R4 to generate new pattern data R5. Next, the CAD system replaces the old data R4 with the new data R5, as shown in FIGS. 9A and 9B. As before, this data replacement is usually performed without trouble, since each of the data R1 to R4 is separated or independent from one the other. Accordingly, pattern data managed in the manner shown in FIGS. 9A and 9B can be easily processed by conventional CAD systems.
Pattern data arrangement, as shown in FIG. 10A, however, presents a problem for conventional CAD systems. The data group S1 shown in FIG. 10A includes individual circuit component pattern data arranged at random. If a CAD system identifies pattern data Sx by window designation, as shown in FIG. 10B, the CAD system then processes the data Sx to generate new pattern data S2. Although the designated pattern data Sx is generally defined by using coordinate values with respect to an origin set on reference pattern other than the pattern Sx, the newly generated pattern data S2 will be defined by new coordinate values with respect to an origin set on the new pattern S2. For this reason, it is impossible, or at least improper to directly replace the old pattern data Sx with the new pattern data S2. This forces the circuit designer to input data necessary to return the new data S2 to the original data group S1. In this type of manual control, the designated pattern data Sx is removed from the data group S1, and the new pattern data S2 is incorporated into the data group S1 to match the remaining data in the data group S1. Should the CAD system have a reverse window function, to automatically perform an operation corresponding to the manual control, the circuit designer still has to recall which window was previously designated for the pattern data Sx. Thus, even with a reverse window function, data organized at random still presents CAD system operations with an inconvenient not present with other forms of data management.